1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a chain-latch circuit having a function equivalent to that of a shift register.
2. Description of the Related Art
When there is a need to supply parallel data to a logic circuit from a data storage after supplying the data serially to the data storage, a shift register is generally used. The shift register is comprised of flip-flops connected in series. Data supplied to the leftmost flip-flop, for example, is transferred to a next flip-flop on the right, and to the next, and so on.
Each flip-flop is comprised eight NAND circuits and two inverters, for example. In this typical circuit configuration, one flip-flop has a circuit size of 10 gates.
In semiconductor integrated circuits, it is generally preferable to implement a given circuit in a chip area as small as possible by employing as small a number of circuit elements as possible. To meet this requirement, a chain latch is suitable since it can be implemented by a small number of circuit elements while achieving an equivalent function to that of a shift register.
FIG. 1 is a circuit diagram of a chain latch.
A chain latch 500 of FIG. 1 includes a plurality of identical memory blocks M connected in series. Each of the memory blocks M receives inputs thereto from the left-hand side of the figure, and supplies outputs therefrom to the right-hand side of the figure. Input data Di0 and Di1 are complementary signals, and so are output data Do0 and Do1.
Each of the memory blocks M includes PMOS transistors 501 through 506 and NMOS transistors 507 through 510. The PMOS transistor 502 and the NMOS transistor 507 together form an inverter. Also, the PMOS transistor 503 and the NMOS transistor 508 together make up an inverter. A pair of the PMOS transistor 504 and the NMOS transistor 509 serves as a gate for controlling whether a signal is transferred therethrough. In the same manner, a pair of the PMOS transistor 505 and the NMOS transistor 510 serves as a gate for controlling whether a signal is transferred therethrough.
With respect to a clock signal CLK, a clock signal XCLK has an opposite phase. When the clock signal CLK is HIGH, therefore, the PMOS transistors 501 and 504 and the NMOS transistors 509 are turned on. In this case, the two inverters together form a latch with each of the inverters receiving as an input thereto an output of the other inverter. This latch holds 1-bit data.
When the clock signal CLK is LOW, the gate comprised of the PMOS transistor 504 and the NMOS transistor 509 is closed, while the gate comprised of the PMOS transistor 505 and the NMOS transistor 510 is opened. Further, the PMOS transistor 506 is turned on. In this case, the inverter on the output side of a given memory block M forms a latch together with an inverter on the input side of a next-stage memory block M, thereby holding 1-bit data.
When the clock signal CLK is changed to HIGH again, the inverter on the input side and the inverter on the output side are connected, and together form a latch within the same memory block M. This latch holds a 1-bit data transferred from the previous-stage memory block M.
In this manner, the chain latch has each memory block M comprised of two inverters, and these two inverters together form a latch to hold data when the clock signal CLK is HIGH (data-hold state). When the clock signal CLK is LOW, the inverter on the output side of a given memory block M forms a latch together with the inverter on the input side of a next-stage memory block M, so that data is held between the two memory blocks M halfway on the transfer route (data-transition state). When the clock signal CLK becomes HIGH again, the two inverters within each memory block M together form a latch, thereby holding data transferred from a preceding-stage memory block M (data-hold state).
As described above, the chain latch implements a function equivalent to that of a shift register by using a relatively small number of circuit elements. Such a chain latch, however, has a problem in that holding of data can become unstable. This is caused by the fact that circuit elements forming latches are altered back and forth between the latches for holding data in the data-hold state and the latches for holding data in the data-transition state during the process of data propagation as the chain latch switches between the data-hold state and the data-transition state.
FIG. 2 is a circuit diagram for explaining the problem of a chain latch. In FIG. 2, the chain latch includes memory blocks M1 through M3. Each of the memory blocks M1 through M3 includes inverters 520 and 521, gates 522 and 523, and PMOS transistors 524 and 525.
Memory blocks of the chain latch are not necessarily arranged in straight line in a semiconductor device. For example, a line of the memory blocks may be folded at a turning point so as to be arranged in two rows in the circuit. I this case, wire lengths between two adjacent memory blocks may be elongated at the turning point, thereby suffering a larger wire capacitance.
In FIG. 2, the memory blocks M2 and M3 are connected via wires (signal lines) N1 and N2, which have wire capacitances (signal-line capacitances) C1 and C2, respectively.
First, a case in which the wire capacitances C1 and C2 are insignificant is considered. As the chain latch switches from the data-hold state to the data-transition state, the gate 523 opens, so that the data held by the memory block M2 appears on the wire N1. The data is input to the inverter 520 of the memory block M3. An output of the inverter 520 is fed back to the input of the inverter 521 of the memory block M2 via the PMOS transistor 525, which is turned on by the clock signal CLK. In the data-transition state, therefore, the inverter 521 of the memory block M2 and the inverter 520 of the memory block M3 together hold data.
When the wire capacitances C1 and C2 are not negligible, it might be possible that the data held by the memory block M2 is destroyed as shown in the following. When the chain latch switches from the data-hold state to the data-transition state, the gate 523 opens, so that the data held by the memory block M2 appears on the wire N1. At the same time as the gate 523 opens, the NMOS transistor 525 is turned on by the clock signal CLK, so that the output of the inverter 520 in the memory block M3 is input to the inverter 521 of the memory block M2. If the capacitances C1 and C2 are negligible as previously described, the data output from the inverter 521 of the memory block M2 changes the status of the inverter 520 of the memory block M3. If the capacitances C1 and C2 are not negligible, it is possible that an output from the inverter 520 of the memory block M3 changes the status of the inverter 521 of the memory block M2, to the contrary to the expectation.
In this manner, when a speed of data propagation is slowed between memory blocks because of an effect of wire capacitances, data on the feedback route can destroy the data held by the memory blocks.
Accordingly, there is a need for a chain-latch circuit which is not susceptible to signal-line capacitances, and can perform expected operations even when a relatively large signal-line capacitance is present.